Power consumption in a System-on-Chip (“SoC”) is categorized as dynamic (also known as active) power and static (or leakage) power. Dynamic power varies with the state of the internal modules or cores (also known as circuit blocks or devices or IPs) and can be controlled by using various methods, for example, clock gating. Static power is controlled by the method of power gating. In power gating, the cores that are not in use by the SoC are temporarily turned off to reduce the overall leakage power of the chip. This temporary shutdown time can also be called “low power mode” or “inactive mode.” When the cores are required for operation they are activated to “active mode.” Thus the known method of power gating minimizes or reduces leakage power by temporarily cutting power off to selective cores that are not required in that mode. However, although power gating saves the leakage power, it may come at the cost of wakeup latency. Typically the CPU may be stalled for several cycles before the gated core can become active. Alternatively, the core could remain active despite any requirement of the CPU to access the core. A SoC consumes some unwanted power in both the scenarios as stated above.